1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to arrangement of the memory cell array of a semiconductor memory device and of the peripheral circuitry which processes the data held in the memory cell array.
2. Description of the Background Art
The chip size of a memory is increased as the memory has larger capacity. Also, as the manufacturing process is increasingly complicated, the number of process steps also tends to be increased. Thus, it has been very difficult to manufacture a memory cell array which does not include even one defective bit. Various approaches have been proposed to overcome this disadvantage. The techniques currently implemented include redundant circuit technique which provides addition of several redundant rows or columns of memory cells to a memory cell array and replacement of a row or column including a defective cell with a redundant row or column.
For example, a non-volatile programming is previously provided so that a spare decoder rather than the regular decoder provides a row select operation for the address signal corresponding to that row of memory cells in a regular array which includes a defective bit. When an address including a defective bit is externally input, the spare decoder is selected and simultaneously a selection prohibiting signal is output to the regular row decoder. Thus, a spare row is selected in place of a regular row.
With such a configuration, data can normally be read and written if a defective bit is present in a memory cell array.
In addition to the redundant circuit described above, parity bit data can also be held for the data held in a dynamic random access memory (DRAM).
As DRAMs have larger capacity, the memory cell area per bit and hence the electric charge stored tend to be reduced. This disadvantageously results in a soft error and the like caused by alpha particles discharged from a radio isotope contained in the materials for chip packages and interconnections. In order to overcome the disadvantage, typically a memory dedicated to parity bit as well as a DRAM are provided on a same board to detect defects. By contrast, a memory chip incorporating a memory cell which holds such a parity bit can detect defects without any other memory chip.
In a DRAM, an Error Checking and Correction (ECC) circuit can be buried in a memory cell array. The memory chip incorporating the ECC circuit can correct error bits and thus significantly improve the reliability of the memory. The incorporation of the ECC circuit into the chip itself also allows reduction of the number of chips on a board for which a system is configured.
To allow for larger capacity memories, a DRAM has also been proposed which has Built-in Self Test (BIST) function, wherein a circuit which produce test data for a chip itself, and a test result discriminator circuit are incorporated in the chip. When a tester inputs a test start signal to the chip, the chip outputs a test result in a predetermined period of time. Application of the BIST function dispenses with an expensive LSI tester and also allows a DRAM to be tested in a short period of time and thus provides an effective approach for testability.
However, the relief of defective bits employing such a redundant circuit as described above is also associated with the following disadvantage: microfabrication of a memory cell array increases the frequency of short-circuit between a word line and a bit line. This defect results in current leakage from the bit line via the word line in the standby operation and thus increases standby current. If the defects of word and bit lines are replaced by means of the redundant circuit, the defect caused by such short-circuit still remains. As an effective approach to the defect, block redundancy technique has been proposed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, No. 11, NOVEMBER 1993, p.1105-p.1112.
According to the block redundancy technique, a defective subarray can be electrically isolated and then replaced with a redundant subarray to reduce unnecessary power consumption and prevent the current leakage caused by short circuit between a word line and a bit line.
Thus, the increment itself of the standby current owing to short circuit between a word line and a bit line can be restricted if the memory capacity is of large scale.
For conventional DRAMs, however, memory array is typically divided into a plurality of regions, such as four regions, for arrangement.
FIG. 17 is a plan view showing an arrangement of a memory cell array in such a conventional DRAM.
A conventional DRAM 302 is configured of memory arrays 304-310 arranged in two rows and two columns, wherein a memory array has a ratio between longer side and shorter side of approximately 1:2.
In such an arrangement of the memory cell array, the distance from the peripheral circuitry to a circuit included in an array is different from that from the peripheral circuitry to a circuit included in another array. Accordingly, all control signals should be designed to be timed, taking into consideration the delay caused between the peripheral circuitry and a circuit in an array which is the most distant from the peripheral circuitry.
Replacement with a redundant column or row of memory cells in memory arrays 304-310, changes the distance from the peripheral circuitry to a circuit to be activated in an array. Accordingly, use of the redundant circuit can require a delayed timing of application of a control signal which is otherwise not delayed in timing.
This implies that while a defective bit itself can be relieved by the redundant circuit, it is necessary to consider the dependence on the time required for transmitting a control signal from the peripheral circuitry to the redundant circuit most distant from the peripheral circuitry in order to maintain a predetermined access time of the DRAM after the replacement with the redundant circuit.